1.
This invention relates to a semiconductor integrated circuit device in which a scan path circuit is self-contained and, more particularly, to a semiconductor integrated circuit device which is adapted to implement a dynamic burn-in test within an LSI device.
With the advent of more advanced minute and precise techniques and with the high integration of LSI circuits, testing of internal circuits for conformity to design is more difficult. It is therefore important to implement a burn-in test for an LSI before shipping to reject initially defective goods and to improve the reliability of products. Especially, a dynamic burn-in test which can be carried out during operation of an LSI is important.
2. Description of the Related Arts
A scan system has been previously proposed as a test method for an internal portion of a large-scaled integration circuit device.
Some examples of the scan system are illustrated in FIGS. 1 to 5. In this scan system, all or several selected flip-flops 3 are connected to each combined internal circuit 2 in an LSI device 1 and a scan-path circuit 7 in which the flip-flops 3 are connected in series in a test mode to form a shift register, is prefabricated in the course of manufacturing LSIs.
In FIG. 1, in a test mode, test data (regarded as scan-in data) SD.sub.IN is scanned-in in synchronization with a scan clock SCCK to arbitrarily determine an internal data state in a shift register. When an operator wants to know an internal active state, a system clock SYSCK is stopped to prohibit a change in the internal active state and the internal data is scanned out serially from a shift register by a series of scan clocks. The scanned-out data SD.sub.out is compared with an expected value produced by a previous simulation to test an occurrence of failure.
FIG 2(b) shows an example of a scan chain combination circuit, wherein flip-flops FF1, FF2 and FF3 form a scan path circuit. An output D.sub.OUT of flip-flop FF1 is input to a combined circuit 2, an output of which is sent to an input D.sub.IN of flip-flop FF2. An output of flip-flop FF3 is input to the combination circuit 2, to thus receive an output of the combination circuit as an input.
A test utilizing a scan path corresponds to a scan clock SCCK from an external portion of a chip, to input a test pattern as an input SD.sub.IN in sequence to the flip-flops (FF1, FF2, FF3). Thereafter, test patterns are input to the combination circuit 2 simultaneously from flip-flops (FF1, FF2, FF3), and a result of the output is held in each flip-flop FF2, FF3. Then a scan clock SCCK is input to output the data held in the external portion of a chip as SD.sub.OUT.
Alexander Miczo discloses a scan path circuit by his book (For example, "Digital Logic Testing and Simulation", Harper & Row Publishers Inc.,). A more advanced scan system using a level-sensitive scan design (LSSD) which can test AC performance, is well known. (For example, refer to ibid, pp. 276-280, and FIG. 7.20)
A still further development has been made in a boundary scan system as shown in FIGS. 3, 4 and 5.
FIG. 5 shows a method of boundary scanning, to verify a connection and a wiring state between a plurality of LSIs on a board, and FIGS. 3 and 4 show a constitution of an I/O cell provided with a function necessary to be applied to the boundary scan method shown in FIG. 5.
An LSI is generally mounted on a printed circuit board (abbreviated by PCB) to implement a system function in association with other LSIs.
As shown in FIG. 5, an LSI (1a) and an LSI (1b) are mounted on a printed circuit board (PCB 6) and the space between the LSI (1a) and the LSI (1b) is connected by a distribution cable 5 on the printed circuit board PCB 6. A prior art boundary scan system provides a method for detecting a fault such as a short-circuit or a disconnection or the like in the wiring 5 in FIG. 5.
FIG. 4 shows an LSI (1a or 1b) of FIG. 5, to be utilized in a boundary scan method. The above-mentioned scan data (SD.sub.IN) is input from each I/O call 26 to which scan data can be input. The scan data is transferred to the nearest I/O call 26, in the order shown by each arrow path 7b. As is shown by a broken line, which is the resultant path, scan data ia transferred and is output from the last I/O cell to the exterior of the LSI, as SD.sub.out.
FIG. 3 illustrates a circuit within the I/O call 26 of FIG. 4. Each boundary scan flip-flop 19 within each I/O cell 26 together forms a scan chain, and in accordance with a scan clock SCCK, an output state of a boundary scan flip-flop 19 in a prior stage of the I/O cell 26 is held, and data D is held in response to a clock CK. A selector 17 selects either of an output A from an internal circuit and an output B of a boundary scan flip-flop 19, and an output buffer 16 produces an output C selected from the selector 17 by a signal .phi..
In a normal operation of the LSI, the selector 17 selects an A side output, to produce an output A of the internal circuit at an external terminal.
In a boundary scan test, the selector 17 selects a B side output, to produce an output B of the boundary scan flip-flop at an external terminal. Under such circumstances, corresponding to an input of scan clocks SCCK, a sequence of scan data SD.sub.IN is transferred to the scan chain, in order to carry out a buffer operation of the output buffer 16, and thus it is possible to produce an output of the boundary scan flip-flop 19 at an external terminal. Further, if a clock CK is input, it is possible to again hold an output state of the boundary scan flip-flop 19.
A brief description of such a detection method will be provided hereinafter.
First, data is latched by serial-shifting data to I/O cells 26a and 26b in the LSI 1a and LSI 1b through boundary scan chains 7b-c, 7b-a, and 7b-b. Then, data is transferred from the LSI 1a to the LSI 1b through the wiring 5. In more detail, data is transferred from the I/O cell 26a to the I/O cell 26b. Finally, data of the I/O cell 26a and I/O cell 26b is read out serially through the scan chains 7b-c, 7b-a and 7b-b. In this case, if a fault occurs in the wiring 5, the data read from the I/O cell 26b is different from the expected value.
Other than the object of using the above-described scan system for detecting a wiring failure on a printed circuit board, the system can also be applied to an implementation of a dynamic burn-in test. The burn-in test as described hereinbefore is carried out in a high temperature environment, in order to detect any initial failures and to improve reliability. In a conventional test, there is a static burn-in test for applying a D.C. bias to an LSI and a dynamic burn-in test for activating an LSI. The dynamic burn-in test for operating an LSI is more effective at detecting initial failures and is more advantageous in that the higher the operating performance is, the more conspicuously the effect is enhanced.
In a conventional example, as shown by an LSI in FIG. 1 in which a scan circuit is self-contained therein, a method is adopted in which a scan clock SCCK and scan data SD.sub.in may be supplied from an external source for improving the operating performance of an LSI in a dynamic burn-in test. However, in the conventional example, only an internal scan circuit is activated and a boundary scan circuit is inactive.
If the above scan circuit is utilized to implement a dynamic burn-in scheme, an external supply of scan data or scan clocks is devised and as a result of this procedure, the following problems will occur.
First, it is necessary to provide a driver for supplying a scan clock SCCK and scan data SD.sub.IN into an LSI device, so that a test device becomes more complicated.
Second, with respect to the drive capacity of a driver, the operating frequency is limited and the fault detection rate is reduced. This results from the fact that the operating frequency reduces and the current flowing through an LSI device drops. The larger the amount of current flowing through an LSI device is, the more the fault detection rate is enhanced.
Third, a test board or a burn-in board for supplying testing signatures into a LSI device is made of a multi-layer type board and a configuration of the device is more complicated and expensive.
Fourth, since an input pin for signals other than scan data and scan clocks in an LSI device is fixed at a HIGH or LOW state, the operation efficiency of an internal gate is reduced in comparison with a case where data is delivered into an LSI device through an input pin. Especially, when a memory circuit is self-contained and an address, data input, control terminal (for write-enable) signals and clocks are delivered directly through an input pin of an LSI device, the memory circuit does not operate at all, even if the input is fixed at a HIGH or LOW state.
Fifth, a layout position of input pins or the like for a scan clock and scan data is fixed to be able to use a burn-in board in common.
It is an object of the present invention to solve the above conventional problems and to provide a semiconductor integrated circuit device for implementing a burn-in test in an LSI using itself as a test object.